1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device fabricated through four photolithography processes and a method of fabricating the same.
2. Description of the Related Art
As shown in FIG. 1, a typical liquid crystal display (LCD) device has a gate bus line 60 arranged in a transverse direction and a data bus line 70 arranged in a longitudinal direction, a thin film transistor (TFT) formed near a cross point of the gate bus line 60 and the data bus line 70. The TFT has a source electrode 70a, a drain electrode 70b, a gate electrode 60a, and a semiconductor layer 80. The drain electrode 70b is connected to a pixel electrode 40.
The LCD device described above is completed through five photolithography processes.
Hereinafter, a method of fabricating the conventional LCD device will be explained in detail. FIGS. 2A to 2E show a process of manufacturing the conventional LCD device, and FIGS. 3A and 3B show a photolithography process to form a gate insulating layer 50, the amorphous silicon (a-Si) layer 80a, and an n-type impurity doped silicon (n+ a-Si) layer 80b. Further, FIGS. 4A-4C show a photolithography process to form source and drain electrode 70a and 70b.
First, a gate electrode 60a shown in FIG. 2A is formed on a transparent substrate 10 during a first photolithography process.
In the first photolithography process, a metal layer (not shown) of Mo or Cr is deposited on the transparent substrate 10 and then a photoresist is applied on the metal layer. Then, a first photo-mask (not shown) is located over the substrate 10, and light exposure and developing processes are performed to etch the metal layer so that the gate electrode 60a is formed. Finally, the photoresist remaining on the metal layer is removed, leaving the gate electrode 60a on transparent substrate 10 as shown in FIG. 2A.
Second, a gate insulting layer 50, the a-Si layer 80a, and a n+ a-Si layer 80b shown in FIG. 2B are sequentially formed during a second photolithography process, detailed as shown in FIGS. 3A and 3B.
As shown in FIG. 3A, a photoresist 88 is applied on the n+ a-Si layer 80b. After that, light exposure and developing processes are performed using a second photo-mask 100, thereby forming a photoresist pattern 88a as shown in FIG. 3B. The a-Si layer 80a and the n+ a-Si layer 80b are simultaneously etched according to the photoresist pattern 88a so that the gate insulating layer 50, the a-Si layer 80a, and the n+ a-Si layer 80b are formed. Finally, the photoresist remaining on the n+ a-Si layer 80b is removed.
Third, the source electrode 70a and the drain electrode 70b shown in FIG. 2C are formed during a third photolithography process, detailed as shown in FIGS. 4A-4C.
As shown in FIG. 4A, a metal layer 170 such as Cr is deposited over the whole surface of the substrate 10 while covering a-Si layer 80a and n+ a-Si layer 80b. After that, the positive type photoresist 88 is applied, and then light exposure and developing processes are performed using a third photo-mask 200, thereby forming a photoresist pattern 88a as shown in FIG. 4B. In accordance with the photoresist pattern 88a, a lower metal layer 170 is etched to form the source electrode 70a and the drain electrode 70b as shown in FIG. 4C. Continually, the n+ a-Si layer 80b is etched using the metal layer (source and drain electrodes) as a mask. Finally, the photoresist pattern 88a remaining on the source electrode 70a and the drain electrode 70b is removed.
Fourth, the passivation layer 55 having the contact hole 30 shown in FIG. 2D is formed during a fourth photolithography process.
An inorganic material such as a nitride or oxide of silicon (SiNx or SiOx, respectively) or an organic material such as bis-benzocyclobutene (BCB) is deposited on the source electrode 70a and the drain electrode 70b. After that, the positive type photoresist (not shown) is applied, and then light exposure and developing processes are performed using a fourth photo-mask (not shown) to form a photoresist pattern. Then, the passivation layer 55 is formed through an etching process. After the etching process, the photoresist pattern remaining on the passivation layer 55 is removed.
Fifth, the pixel electrode 40 to be connected to the drain electrode 70b shown in FIG. 2E is formed during a fifth photolithography process.
A metal layer such as indium tin oxide (ITO) is deposited on the passivation layer 55. After that, the positive type photoresist (not shown) is applied, and then light exposure and developing processes are performed using a fifth photo-mask (not shown), thereby forming a photoresist pattern. In accordance with the photoresist pattern, the metal layer is etched so that the pixel electrode 40 is formed. After the etching process, the photoresist pattern remaining on the pixel electrode 40 is removed.
The photolithography process described above includes the steps of: cleaning a substrate; applying a photoresist; soft-baking the photoresist; aligning a photo-mask; light-exposing the photoresist; developing the photoresist; inspecting the array substrate; hard-baking the photoresist; etching a portion that the photoresist does not cover; inspecting the array substrate; and removing the photoresist.
Since the photolithography process includes the complex steps described above, as the number of photolithography processes increases, the inferiority rate become greater, leading to a low yield. In other words, reliability of the manufacturing process varies inversely proportional to the number of photolithography processes performed.